Modeling Instruction-Level Parallelism for Software Pipelining

Software pipelining is an attractive method to schedule code for processors that exhibit instruction-level parallelism such as pipelined, super-scalar, and (V)LIW machines. It has been implemented for a variety of processors ( e.g. FPS-164[10], Warp[9], Cydra-5[7]), and a number of pipelining algorithms have been described in the literature. Software pipelining produces a schedule so that the executions of multiple loop iterations are overlapped. Operations from multiple loop iterations are either placed into the same instruction word, or are interleaved, depending on the type of instruction-level parallelism provided in the target architecture. In contrast to other scheduling techniques that rely on loop unrolling to determine the number of iterations to overlap, the degree of overlapping in software pipelining is determined by the exact resource requirements of the loop operations. Thus, accurate modelling of machine resources is especially crucial for software pipelining. Modelling the target machine is easy for idealized machines, but for a real processor, a number of challenges arise. For example: